I've always loved my Thinkpad X220, but I've also always been bugged by its grainy 1360x768 display. Recently I ordered nitrocaster's FullHD mod and retrofitted my X220 with a shiny new 1920x1080 IPS display - boy what a difference. All is well?
Unfortunately, no. nitrocaster's mod connects to the eDP port, which leaves the LVDS port of the original display dangling in the air. Linux sees two display connectors that you have to mirror - with all sorts of ugly side effects. There is a way to get rid of the LVDS output however: replace the Lenovo BIOS with coreboot and disable LVDS in the firmware. There is a patch that does exactly that for the X230 that I could frankenstein into the X220 coreboot branch.
Here's what you have to do to get an X220 LVDS-free coreboot bios:
- git clone my coreboot fork and checkout the x220_fhd branch.
- follow any of the numerous X220/X230 coreboot tutorials to get your coreboot toolchain running.
- as dwhacks noted over here, the submodules in my repo don't have a coreboot URL any more and hence don't work. Run the following commands in the coreboot directory to fix this:
for i in `\ls -1 3rdparty/` ; do git rm 3rdparty/$i ; done git rm util/nvidia/cbootimage/ git rm coreboot git submodule add https://github.com/coreboot/blobs.git 3rdparty/blobs git submodule add https://github.com/coreboot/nvidia-cbootimage.git util/nvidia/cbootimage git submodule add https://github.com/coreboot/vboot.git 3rdparty/vboot git submodule add https://github.com/coreboot/arm-trusted-firmware.git 3rdparty/arm-trusted-firmware git submodule add https://github.com/coreboot/libhwbase.git 3rdparty/libhwbase git submodule add https://github.com/coreboot/libgfxinit.git 3rdparty/libgfxinit git submodule add https://github.com/coreboot/fsp.git 3rdparty/fsp
- use a raspi or CH341A programmer to extract your original BIOS image.
- again following any of the tutorials, extract descriptor.bin, me.bin and gbe.bin and neuter Intel ME if you're so inclined. Then copy descriptor.bin, me.bin and gbe.bin to 3rdparty/blobs/mainboard/lenovo/x220/.
- use this guide to extract the VGA BIOS. Name it vgabios.bin. I could not get any coreboot/Seabios output without this.
- make nconfig to configure coreboot. The relevant parts are:
*** Important: Run 'make distclean' before switching boards *** Mainboard vendor (Lenovo) ---> Mainboard model (ThinkPad X220 Nitrocaster Full HD mod) ---> ROM chip size (8192 KB (8 MB)) ---> System Power State after Failure (S5 Soft Off) ---> (0x100000) Size of CBFS filesystem in ROM () fmap description file in fmd format
[*] Set IA32_FEATURE_CONTROL lock bit Include CPU microcode in CBFS (Generate from tree) ---> *** Northbridge *** [*] Use native raminit [*] Ignore vendor programmed fuses that limit max. DRAM frequency [ ] Ignore XMP profile max DIMMs per channel *** Southbridge *** [*] Lock down chipset in coreboot Flash locking during chipset lockdown (Don't lock flash sections) ---> *** Super I/O *** *** Embedded Controllers *** [*] Beep on fatal error [*] Flash LEDs on fatal error [*] Support bluetooth on wifi cards *** Intel Firmware *** [*] Add Intel descriptor.bin file (3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin) Path and filename of the descriptor.bin file [*] Add Intel ME/TXE firmware (3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin) Path to management engine firmware [*] Verify the integrity of the supplied ME/TXE firmware [*] Strip down the Intel ME/TXE firmware *** Please test the modified ME/TXE firmware and coreboot in two steps *** [*] Add gigabit ethernet configuration (3rdparty/blobs/mainboard/$(MAINBOARDDIR)/gbe.bin) Path to gigabit ethernet configuration Protect flash regions (Unlock flash regions) ---> Bootblock behaviour (Always load fallback) --->and
Graphics initialization (Use libgfxinit) ---> Display ---> -*- Enable PCIe Common Clock -*- Enable PCIe ASPM [*] Enable PCIe Clock Power Management [*] Enable PCIe ASPM L1 SubState [ ] Early PCI bridge (0x0000) Override PCI Subsystem Vendor ID (0x0000) Override PCI Subsystem Device ID [*] Add a VGA BIOS image (vgabios.bin) VGA BIOS path and filename (8086,0126) VGA device PCI IDs [ ] Add a discrete VGA BIOS image [*] Add a Video Bios Table (VBT) binary to CBFS (src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt) VBT binary path and filename [ ] Enable I2C controller emulation in software
Display ---> needs to be set to Framebuffer mode (Legacy VGA text mode).
Make sure to choose the correct paths for the firmware blobs and the VGA BIOS.
You can also download my config file (rename to .config).
- make to compile coreboot
- flash it!
Update: by default the nitrocaster PCB is powered by a constant VCC line (the power cable you just soldered on, remember?), which leads to a rather high power consumption in sleep mode. This can be fixed by removing the power cable, shorting J1 on the nitrocaster PCB and using my coreboot fork with commit 840a47e applied. coreboot then controls power rail VCC3P which supplies the nitrocaster board. This way my suspend battery drain is < 1%/h, even on my 8 year old battery - nice!